OK, enough with octa-core mobile monstrosities for now. Let’s shift gears to Embedded World 2014 and the lower end of the spectrum, one that will make up the vast majority of devices on the Internet of Things: tiny, low power microcontrollers with integrated wireless connectivity.
There still seems to be some stigma about putting RF into designs, and some of it is justified. One of our readers commented this week that Apple “does not have the know-how” in reference to integrated baseband LTE. On the contrary, I’d say: Apple can buy any IP or talent they want. Their reluctance stems more from the realities of supply chains and multiple carrier qualifications facing different requirements in worldwide markets, not a technology issue per se.
RF designs still need proper care and feeding and regulatory clearance. We continue to see strides in RF integration – with attention now turning to
A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design. The designers should be able to easily analyze different parts of the design which can be in different languages such as Spice, Verilog, VHDL, SystemVerilog etc. and can have different levels of voltages and signals.
Last week I attended a webinar (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/page.php?s=e) on Mixed Signal SoC Verification hosted by EDA Direct (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.edadirect.com/) where they showcased StarVisionTM tool from Concept Engineering (http://www.semiwiki.com/cgi-bin/clickthru.pl?http://www.concept.de/)
10313Since Synopsys acquired Eve over a year ago, they haven’t announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new “release” is a complete re-design using new hardware fabric in a new process technology. Earlier this week Synopsys announced Zebu Server-3, currently the industry’s fastest emulation system (to be fair, whenever a new emulation product is announced it tends to be the fastest for a time…). They also announced a collaboration with Imagination Technologies to enable faster emulation, currently for Imagination’s PowerVR GPUs and in the future for the MIPS processor line too. Imagination are achieving clock speeds of 3.5MHz emulating their GPUs, compared to historic speeds closer to 1MHz with earlier generations of emulators.
10314ZeBu servers come in a 20” cube weighing 155lbs and consuming less than 2.5KW. Inside there are Zebu modules (boards)
In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for clock lines, or any other place there is critical interconnect in high speed analog or RF circuits.
Several things have changed that are now compelling designers to look more closely at interconnect parasitics. Up until now inductance was something that could be ignored. But with higher frequencies, even simple wires inside circuits are starting to look like transmission lines. The rule of thumb has been that when the length of the signal path was long enough to become some percentage of a wavelength that the line itself starts to become a concern for signal integrity. The question is
Did you know in the Xilinx Virtex 28nm series you can REALLY run the DSP at 741 MHz? I say ‘really’ as you know dear reader, not all the FPGA claims of speed and usage tends to live up to reality. I cannot stand marketing games where you can run at a GHz ‘But’ and then comes the list of gotcha’s. Don’t believe me? Whaaat? Well let’s take a journey through a REAL example of a Parallel FIR filter that runs in REAL silicon TODAY running the DSP at 741 MHz. By the way, my kids laugh every time I say FIR filter.
Why did the digital filter designer get attacked by ‘People for the Ethical Treatment of Animals’?
‘He was selling FIRs’.
I know my poor kids, once again please pray.
So let us begin, what is a FIR filter? ‘FIR’ stands for Finite Impulse Response. DSP 101. They are the heart of